| PART |
Description |
Maker |
| NB4L339MNG NB4L339MNR2G NB4L33907 |
2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan−Out Buffer
|
ON Semiconductor
|
| MC100LVE222 MC100LVE222FAR2 ON0511 MC100LVE222FA |
0.345A, 2.7-5.5V Quad (2In/ 4Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 16-SOIC 0 to 85
Low Voltage 1:15 Differential ±1±2 ECL/PECL Clock Driver
From old datasheet system
MARKING DIAGRAM
Low Voltage 1:15 Differential 12 ECL/PECL Clock Driver
Low Voltage 1:15 Differential ÷1÷2 ECL/PECL Clock Driver
|
ONSEMI[ON Semiconductor]
|
| NB4L339 |
2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator
|
ON Semiconductor
|
| CY2PP3220AI CY2PP3220AIT CY2PP3220 |
Dual 1:10 Differential Clock/Data Fanout Buffer
Dual 1:10 Differential Clock / Data Fanout Buffer 2PP SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
|
CYPRESS[Cypress Semiconductor]
Cypress Semiconductor, Corp.
|
| SI5330A-A00200-GM SI5330A-A00202-GM SI5330F-A00216 |
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs
|
Silicon Laboratories
|
| MC100ELT23 MC100EL12DTR2 MC10H131FNR2 MC100H640FNR |
5V Dual Differential PECL to TTL Translator
5V ECL Low Impedance Driver
Dual Type D Master-Slave Flip-Flop
ECL/TTL Clock Driver
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V / 5V ECL ÷4 Divider
Quad 2-Input NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
3.3V / 5V Hex Differential Line Receiver / Driver
3.3V / 5V Triple ECL Input to LVPECL/PECL Output Translator
|
ON Semiconductor
|
| MC100EP01 MC10EP445 MC10H172FNR2 MC100EL29 MC100H6 |
3.3V / 5V ECL 4-Input OR/NOR
3.3V / 5VECL 8-Bit Serial/Parallel Converter
Dual Binary 1-4-Decoder (High)
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
9-Bit TTL-ECL Translator
Quad TTL-ECL Translator
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
3.3 V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
3.3V 10-bit LVTTL/LVCMOS to LVPECL Translator
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
5V ECL Voltage Controlled Oscillator
3.3V ECL D-Type Flip-Flop with Set and Reset
Binary to 1-8 Decoder (Low)
Differential -5V ECL To TTL Translator
-3.3V / -5V Triple ECL Input to PECL Output Translator
5V ECL Dual Differential 2:1 Multiplexer
Quad MSTR
5V ECL Quad 4-Input OR/NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
Dual 4-5-Input OR/NOR
|
ON Semiconductor
|
| NBSG53A-D |
2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS*
|
ON Semiconductor
|
| NB4L339 |
Clock IN to Differential LVPECL Clock Generator
|
ON Semiconductor
|
| NB100LVEP224FAG |
2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable 100LVE SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
|
ON Semiconductor
|
| HDMP-1637A |
HDMP-1637A · 1.25 GBd SerDes Circuit with Differential PECL Clock Inputs for Gigabit Ethernet Applications
Gigabit Ethernet SerDes Circuit with Differential PECL Clock Inputs
|
Agilent (Hewlett-Packard)
Agilent(Hewlett-Packard)
|
